Industry standard low-power memory interfaces typically employ single-ended signaling without termination at the receiving end of the channel, thus avoiding power-consuming DC current flow through the termination loads. However, this approach can effectively limit signaling bandwidth. A number of techniques have been employed to extend signaling bandwidth while reducing DC termination current. In one approach, for example, termination loads are coupled between respective signaling lines and a signaling supply voltage (e.g., Ground or VDD) to eliminate the DC current path for one of the two channel polarity states (high or low). Complementary techniques, such as bus-invert coding, help reduce the aggregate bus current by using an additional line to encode the polarity of the bus. Unfortunately, even when employed together, supply-voltage termination referencing and bus-invert coding still result in relatively high DC power consumption (i.e., they reduce the maximum DC current of signaling line by only 50%) and such schemes incur the added expense of an additional signal line for bus encoding purposes.